The present invention is related to electrical logic devices, and in particular to dynamic logic devices.
Dynamic logic circuits utilizing static “keeper” circuits offer an alternative to static logic in situations where increased circuit bandwidth (speed) is desired. FIG. 1 shows an exemplary prior art dynamic logic circuit 100 including a pull-up transistor 110 operating as a keeper circuit. In particular, dynamic logic circuit 100 is a three input OR gate (IN0, IN1, IN2), with another input (IN3) operating as an enable by application to the gate of an enable transistor 160. The logic function implemented by dynamic logic circuit 100 is OUT=(IN3 & (IN0 OR IN1 OR IN2)). Dynamic logic circuits are also available for implementing other logic functions.
In operation, a precharge input 130 may be asserted low shortly before a transition of IN3 to turn on a precharge transistor 132. This allows current from a supply 140 to be available at an input of a buffer 150 and provides for relatively quick switching of an output 120. When IN3 is asserted high, output 120 is set to a logic state reflecting the state of IN0, IN1, IN2. In particular, whenever at least one of IN0, IN1, IN2 are set at a logic ‘1’, respective logic transistor(s) 102, 104, 106 are turned on causing the voltage at an input of an inverting buffer 150 to go to approximately ground. This results in a logic ‘1’ at output 120 because of the inverting nature of inverting buffer 150. Otherwise, the voltage at the input of inverting buffer 150 is forced to approximately the voltage of supply 140 as precharge transistor 130 is turned on.
Pull-up transistor 110 is switched off whenever output 120 is set at a logic ‘1’. In contrast, when output 120 is set at a logic ‘0’ and precharge transistor 132 is turned on, pull-up transistor 110 is switched on. When, however, precharge transistor 132 is turned off and enable transistor 160 is turned off, the input of inverting buffer 150 floats at a level that causes pull-up transistor 110 to be switched off, but at a level that is just below that required to turn on pull-up transistor 110. In this way, dynamic logic circuit 100 is capable of producing very fast edges and relatively high bandwidth operation.
For fastest operation, the size of pull-up transistor 110 is minimized. However, to assure stability, the size of pull-up transistor 110 is typically substantially larger than enable transistor 160. This provides an ability to pull-up substantially more through pull-up transistor 110 than the offsetting pull-down through enable transistor 160. While this increases stability, it also substantially increases the amount of leakage current associated with pull-up transistor 110. As the voltage of supply 140 is decreased to implement different logic technologies, an increasing portion of the power consumption of dynamic logic circuit 100 corresponds to the aforementioned leakage current. Power expended through leakage current is undesirable.
Thus, for at least the aforementioned reason, there exists a need in the art for advanced dynamic logic devices and systems, and methods for implementing and utilizing dynamic logic.